The parent application identified above describes a new cluster architecture for high-speed computer processing systems, referred to as supercomputers. For most supercomputer applications, the objective is to provide a computer processing system with the fastest processing speed and the greatest processing flexibility, i.e., the ability to process a large variety of traditional application programs. In an effort to increase the processing speed and flexibility of supercomputers, the cluster architecture for highly parallel multiprocessors described in the previously identified parent application provides an architecture for supercomputers wherein a multiple number of processors and external interface means can make multiple and simultaneous requests to a common set of shared hardware resources, such as main memory, secondary memory, global registers, interrupt mechanisms, or other shared resources present in the system.
One of the important considerations in designing such shared-resource, multiprocessor systems is to provide an efficient mechanism for processors and external interface ports to signal other processors and external interface ports. As used within the present invention, the term signal refers to the operation by which one device (processor or external interface port) indicates to another device that an event has occurred that requires action or intervention by the device being signaled. From a traditional software perspective, signals are more commonly referred to as interrupts in the sense that the operational flow of the device is interrupted to process the signal.
Many parallel processor architectures implement signals as messages passed through the system on a common bus or channel, such as in the Intel iPSC Concurrent computer or in the Sequent Balance Series. In this type of architecture, message transmission can take milliseconds for any processor to interrupt another in the system, largely due to the overhead associated with assembling, transmitting, and interpreting a complex message structure. This overhead is a limitation of this type of signaling architecture.
Other parallel processor architectures do not permit signals to be sent and received by peripheral controllers. In this architecture, processors are dedicated to communicating with input/output devices such that an input/output device can communicate only with the processor to which it is connected. This restriction limits the flexibility for assigning processors to input/output control tasks.
Another problem with many of the present interrupt mechanisms for multiprocessor systems is that all of the processors in the multiprocessor system are unconditionally interrupted at the completion of an input/output activity, not just the processors associated with controlling that activity. The disadvantage to this technique is that all programs executing on the multiprocessor system are interrupted which wastes processor resources while the interrupt are being serviced by one of the processors.
Although the prior art interrupt mechanisms for multiprocessor systems are acceptable under certain conditions, it would be desirable to provide a more effective interrupt mechanism for a multiprocessor system that was able to allow a process to select any individual interruptable resource to be the targeted handler for servicing a signal. In addition, it would be desirable to provide an interrupt mechanism for the cluster architecture for the multiprocessor system described in the parent application that aids in providing a fully distributed, multithreaded input/output environment.